Over the last decade gallium nitride (GaN) high electron mobility transistors (HEMTs) have developed rapidly for use in power electronics and high power, high frequency (generally referred to as Radio Frequency (RF)) applications. In high power, high frequency applications, Monolithic Microwave Integrated Circuit (MMICs) have demonstrated power amplifiers (PAs) and low noise amplifiers (LNAs) with excellent characteristics at frequencies ranging from S-band to W-band and beyond. In general, the GaN PAs exhibit gain and efficiencies equivalent to GaAs PAs at ≧5 times the power density and often with very large output peripheries. This combination of power density and periphery in turn leads to MMICs with very large total output power.
The high power density and total output power have posed reliability challenges (electrical and thermal) that have had to be solved at the material, device, on-chip interconnect, and module levels. Compound semiconductor foundries have spent the last decade addressing these issues largely successfully. In the case of on-chip interconnect (metal wiring), for instance, electro-migration resistant gold (Au) based transmission line fabrication processes have had to be developed for demanding continuous wave (CW) and pulsed high power RF applications.
However, as GaN device technology matures and proliferates into commercial and defense markets, cost reduction efforts will become increasingly more important. To that end, manufacturing GaN devices in a silicon (Si) foundry with high yield subtractive processes, large diameter wafers, and a (Moore's law based) culture of rapid development is a natural evolutionary path for the technology. However, gold (Au) based wiring schemes are not compatible with silicon foundries due to both the high cost of Au and the fact that Au is essentially a contaminant in Si CMOS based processes. Instead of Au, advanced silicon foundries use copper (Cu) interconnect technology. As a result, new approaches will be needed to prevent electro-migration induced failures in copper (Cu) interconnects for high power RF MMICs.
As is known in the art, copper-based digital integrated circuit chips typically use copper interconnects because copper (Cu) is a better conductor than aluminum (Al). A secondary benefit, however, is that Cu is more resistant to electro-migration. Electro-migration, the process by which a metal conductor changes shape under the influence of an electric current flowing through it (and which eventually leads to the breaking of the conductor), is significantly better with copper than with aluminum (another metal option typically available in silicon foundries). This improvement in electro-migration resistance allows higher currents to flow through a given size copper conductor compared to aluminum. However, copper requires a different method for patterning than aluminum because the lack of volatile copper compounds stifles plasma dry etching of Cu metal lines for interconnects. Therefore, the patterning of the copper is done using an additive patterning process, sometimes referred to as “Damascene” or “dual-Damascene” process by analogy to a traditional technique of inlying metal into a host material, see U.S. Pat. Nos. 6,342,733 and 7,259,090 and U. S. Patent Application Publication No. 2014/0183739. Still more particularly, in this process, a host insulator material for the copper, typically an underlying insulating layer, is patterned with open trenches where the copper is to be formed. A thick coating of copper that significantly overfills the trenches is deposited on the insulating layer, and chemical-mechanical planarization (CMP) is used to remove the excess copper that extends above the top of the insulating layer. Copper sunken within the trenches of the insulating layer is not removed and becomes the patterned conductive interconnect.
Damascene processes generally form and fill a single feature with copper per Damascene level (or stage) of the metal interconnect (which may be disposed as horizontal trenches or vertical vias). For the single Damascene variant of Back End of Line (BEOL) circuit fabrication, this proceeds using a base dielectric stack having a silicon nitride (SiNx) etch stop (to limit metal interconnect trench depth) and silicon oxide (SiOx in which trenches are formed) followed by diffusion barrier and Cu deposition into the trenches and Cu CMP (as outlined above). It is noted that the SiNx and SiOx layers have compositions with x>0. The process then repeats to facilitate multilevel interconnect formation.
Dual-Damascene processes generally form and fill two features with copper at once, e.g., a trench overlying a via level (or stage) of the electrical interconnect structure may both be filled with a single copper deposition using dual-Damascene. Thus, with a dual Damascene process interconnect the level or stage and the via level or stage of the electrical interconnect structures are formed with one fill of copper. A barrier metal layer must completely surround all copper interconnections, since diffusion of copper into surrounding materials would degrade their properties. As the name implies, a barrier metal must limit copper diffusivity sufficiently to chemically isolate the copper conductor from the insulating material below, yet have high electrical conductivity in order to maintain a good electronic contact. The barrier layer also must act as an adhesion layer between the Cu and underlying dielectric and metal layers.
As is also known in the art, while copper metallization utilizing Damascene processing has become the dominant interconnection processing in manufacturing digital and other relatively low power integrated circuits (ICs). Damascene processing has also been used in the fabrication of RF amplifier power circuits having electrical interconnects such as, microwave transmission lines, for the RF transistors and passive matching structures of a Monolithic Microwave Integrated Circuit (MMIC). One such MMIC Damascene electrical interconnect structure is shown in FIG. 1. Here, for example, microwave energy is fed through an input microwave transmission line, here a strip transmission line having a strip conductor separated from a ground plane conductor by a dielectric structure, to the gate electrode (G) of an amplifier GaN FET through a capacitor, here for example, a Metal Insulator Metal (MIM) capacitor; the FET having a grounded source electrode (S); the drain electrode (D) being coupled to an output microwave transmission, here a strip transmission line having a strip conductor separated from a ground plane conductor by a dielectric structure, as indicated. The following paragraphs outline the generalized formation of a MMIC employing single Damascene Cu BEOL formation.
After formation of gate (G), source (S), and drain (D) of the core transistor, the transistor is covered with the Damascene base dielectric stack (typically silicon nitride (SiN) etch stop and silicon oxide (SiOx) as mentioned previously) and back end of line (BEOL) formation of the integrated circuit (IC) proceeds, FIG. 1. The first via level (V0) is formed in the base dielectric stack to provide electrical connection to the first metal level M1. Next, another base dielectric stack is deposited and used to form the first metal level M1 providing the ground plane conductor, the bottom plate of the capacitor. Next, another base dielectric stack is deposited for and the capacitor top and Via 1 are formed and then metallized concurrently. This is then followed by the deposition of another base dielectric stack and formation of the second metal layer M2. It is noted that V1 provides: the upper plate for the capacitor; provides a portion of the connection between the strip conductor of the input microwave transmission line and the bottom plate of the capacitor; provides a portion of the connection between the gate electrode (G) and the top plate of the capacitor; and provides a portion of the connection between the drain (D) electrode and the strip conductor of the output microwave transmission line. The process continues with the next base dielectric layer stack with open vias to form via V2. This in turn followed another base dielectric stack and trench formation and metal deposition to form the third metal layer M3. It is noted that V2 provides: a portion of the connection between the strip conductor of the input microwave transmission line and the bottom plate of the capacitor; provides a portion of the connection between the gate electrode (G) and the top plate of the capacitor, and provides a portion of the connection between the drain (D) electrode and the strip conductor of the output microwave transmission line. The third metal layer provides the strip conductors, as shown.
It should be noted that other passive devices, not shown, such as thin film resistors and spiral inductors may be formed using the metal levels M2 and M3. Furthermore different circuit topologies (such as GaN MMICs integrated with Si CMOS circuits by wafer bonding) may require more or less levels of metal than are shown here. Finally, after final metal deposition, SiNx and SiOx capping layer depositions are typically performed followed by final interconnect formation for packaging or test.
The inventors have recognized that one of the reasons for using upper level metals for passive RF circuitry is they are typically the thickest metals formed during Damascene process, for example, 3 microns thick. With these thicker metals, RF or microwave transmission line loss can be lower in addition to handling high power when compared to the lower thinner metals. For example in RF power amplifier IC's the AC power output of several transistors will typically be combined to a single point before going off chip. This power combining is achieved by joining several microwave transmission lines. This thick metal interconnect layer or level (the microwave transmission lines) for level (or stage) M3 is typically 3 to 7 microns thick of un-interrupted copper bounded by the barrier layer used in the Damascene process on the bottom and top of metal for stage or level M3. One reason being that the thickest available un-interrupted bulk conductor of the metal interconnect layer will handle the most power will reduce the chances of high power microwave transmission line failure.
As is also known in the art, one type of photolithgraphically formed MMIC conductor is described in U.S. Pat. No. 5,646,450, inventors Liles et al., issued Jul. 8, 1997. Here, a semiconductor structure is described having a first electrode and a second electrode disposed on a surface of the structure and a bridging conductor connected between the first electrode and the second electrode. The bridging conductor includes a plurality of layers of different metals wherein the plurality of layers of different metals includes a layer of refractory metal adjacent a layer of electrically conductive metal. In a preferred embodiment, the refractory metal is titanium and the electrically conductive metal is gold. With such an arrangement, a semiconductor structure is provided which is effective in preventing restructuring due to mechanical stresses induced in the metal by dissimilar thermal expansion coefficients when electrical pulsing cycles (as when propagating microwave energy) the temperature of the semiconductor structure.
The inventors have recognized because most of the RF energy propagates closer to the surface of the metal interconnect layer (known as the skin effect), this is where the greatest temperature excursions and cycling of the bulk copper will occur and be a source of microwave transmission line failure. For example the skin depth for a 5 GHz signal is approximately 1 micron for bulk copper. Since most of the RF energy propagates closer to the surface this is where the greatest temperature excursions and cycling of the bulk copper will occur and be a source of microwave transmission line failure.
More particularly, the inventors have recognized that a single strip conductor can formed as multi-layer stack specifically designed with prevent electro-migration of the Cu metal wire under high power applications. In accordance with the disclosure, the inventors use a thin electrically conductive barrier layer (typically used for adhesion and to prevent Cu diffusion), and the thicker Cu layer (used for carrying current) and design a structure of stacked barriers and Cu layers such that the barrier layer also serves to prevent restructuring of the Cu (in addition to preventing Cu diffusion.
Thus, in accordance with the disclosure, a microstrip transmission line is provided comprising: a dielectric structure; and, a strip conductor disposed over the dielectric structure, the dielectric structure having open ended trench therein. The strip conductor is disposed in the trench. The strip conductor comprises a plurality of stacked metal layers disposed in the trench. The stacked metal layers have disposed on bottom and sidewalls thereof conductive barrier metal layers.
In one embodiment, each metal stack in the strip conductor is comprised of a thin conductive barrier layer (which itself may be a plurality of thin metal layers) followed by a thicker layer of Cu.
In one embodiment, a semiconductor structure is provided comprising: a semiconductor layer having an active device therein; a dielectric structure disposed over the semiconductor layer, such dielectric structure having open ended trench therein; an electrical interconnect level disposed in the trench and electrically connected to the active device; a plurality of stacked metal layers disposed in the trench; wherein such stacked metal layers have disposed on bottom and sidewalls thereof conductive barrier metal layers.
Thus, while the upper most metal interconnect for layer M3 of the MMIC of FIG. 1 is formed as a homogenous Damascene copper conducting interconnect layer, in accordance with one embodiment of the disclosure, this upper Damascene for stage or level M3 copper metal interconnect layer is formed as a stack of Damascene interconnect layers, each Damascene interconnect layer having a thin copper layer between a pair of barrier seed layers for the copper in the copper layer thus reducing the temperature fatigue of this Damascene metal interconnect metal for stage or level M3 of FIG. 1. Further, the inventors have recognized that the Damascene process may therefore be all the way from bottom via (Via-0) metal interconnect layer of the MMIC (FIG. 1) through to last Cu Metal interconnect stage or level (M3) and that the barrier seed layers can be used to control metal restructuring. Thus, the inventors have recognized that replacing the solid thick interconnect metal stage or level M3 of un-interrupted copper with a plurality of thinner stacks of barrier layers and copper layers (each one of the layers having a lower barrier metal layer) that the power handling power of the upper metal interconnect layer under extreme temperature cycling as when carrying microwave energy may be improved. Thus, the inventors have recognized that the Damascene process already used to form a single metal interconnect for each stage or level can be used as a sequence of a plurality of individual Damascene processes to form each metal interconnect as a stack of thinner metal layers itself thereby improving the power handling power of the upper metal interconnect layer under extreme temperature cycling as when carrying microwave energy.
In one embodiment, a similar multi-layer structure could be formed in a single step trench through repeated deposition stacks of barrier metal and Cu in that trench followed by a single CMP step following metal deposition.
In one embodiment, the metal layers are copper.
In one embodiment, the barrier layer is Ta, TaN, TiN or combination thereof.
In one embodiment the dielectric structures is aluminum nitride.
In one embodiment, an electrical interconnect structure is provided having: a pair of vertically positioned, horizontally disposed, dielectric structures, each one of the dielectric structures having a plurality of open ended trenches therein, each one of the trenches in at least one of the dielectric structures including therein an electrical interconnect level having a lower portion thereof terminating in an upper portion of an electrically conductive via passing through a lower one of the dielectric structures to interconnect with an electrical interconnect level in a trench in the lower one of the dielectric structures, and wherein said electrical interconnect level at least one of the dielectric structures comprises a plurality of metal layers, each one of the metal layers having a barrier metal on side walls thereof.
In one embodiment, a structure is provided having: a pair of vertically positioned dielectric structures, an upper one of the dielectric structures having an open ended trench therein and a lower one of the pair of dielectric structures having an electrically conductive via passing there through; and an electrical interconnect disposed in the open ended trench, the electrical interconnect level having a lower portion terminating in an upper portion of the electrically conductive via, the electrical interconnect level a plurality of metal layers, each one of the metal layers having a barrier metal on side walls thereof.
In one embodiment, a semiconductor structure is provided having: a semiconductor layer having an active device therein; a dielectric structure disposed over the semiconductor layer, such dielectric structure having open ended trench therein; an electrical interconnect level disposed in the trench and electrically connected to the active device; a plurality of stacked metal layers disposed in the trench; wherein such stacked metal layers have disposed on bottom and sidewalls thereof conductive barrier metal layers have disposed on bottom and sidewalls thereof conductive barrier metal layers.
In one embodiment, a semiconductor structure is provided having: a semiconductor layer having an active device therein; a passive device formed over different portions of the semiconductor layer, a plurality of vertically positioned, horizontally disposed, dielectric structures over the semiconductor layer, each one of the dielectric structures having a plurality of open ended trenches therein, each one of the trenches in at least one of the dielectric structures including an electrical interconnect level electrically connected to one of the active and passive devices, wherein said electrical interconnect level in said at least one of the dielectric structures comprises a plurality of stacked metal layers, such layers have disposed on bottom and sidewalls thereof conductive barrier metal layers.
Like reference symbols in the various drawings indicate like elements.